The present invention relates to a semiconductor integrated circuit provided with a memory and more particularly to a technology for reducing leakage currents in memory cells in low-power consumption state, such as standby state, which is applicable to, for example, a microcomputer provided with a large-capacity ROM.
There is a technology for reducing power consumption and yet preventing increase in access delay. According to this technology, the substrate bias voltage of a peripheral circuit when DRAM is active is made different from that when the DRAM is on standby. Thereby, sub-threshold leakage in the memory peripheral circuit on standby is suppressed and the above object is attained. (Refer to Patent Document 1.)
According to another technology, the bit lines and the source lines of memory cells unselected for access when a memory is active are brought to a bit line potential. Thereby, sub-threshold leakage in the memory cells unselected for access is suppressed. (Refer to Patent Document 2.)
[Patent Document 1]    Japanese Patent Prepublication No. Hei 8(1996)-83487
[Patent Document 2]    Japanese Patent Prepublication No. Hei 4(1992)-74395